1. Field of the Invention
This invention relates to a microprocessor, and particularly relates to a cache memory unit characterized by its cache replacement control when the incorporated cache memory misses.
2. Description of the Prior Art
Recent microprocessors tend to incorporate a cache memory for speedy memory access. Microprocessors, however, require a number of control circuits inside and the cache memory capacity cannot be more than a few kilobytes due to limitation imposed by chip size. This results in a low hit ratio at present. Under such circumstances, what determines the performance of a microprocessor with an incorporated cache memory is the time needed to update the cache memory with data retrieved from main memory when a cache miss occurs.
In a typical microprocessor with incorporated cache memory, an instruction code is transferred from a cache memory unit to an instruction decoding unit via an internal data bus. When capable of processing another instruction code, the instruction decoding unit requests the cache memory unit to provide the next instruction code.
Retrieval from the cache memory is performed according to the contents on the internal address bus. If the cache memory hits, the data in the cache memory is output to the internal data bus. If the cache memory misses, the cache control circuit requests a cache replacement and the bus timing control circuit activates bus cycles for access to an external main memory for cache replacement. The data read from the external main memory is output to the internal data bus and then registered or written to the cache memory.
Next, the cache replacement operation is described. When the cache memory hits, the internal address is updated by an address updater and kept at a prefetch pointer. If the cache memory misses, the prefetch pointer holds the internal address which caused the cache miss until the completion of bus cycles and outputs the replacement address to the cache memory.
When the cache memory hits, the internal data contained in the cache is immediately output to the internal data bus, but when it misses, the data accessed from the external main memory during a bus cycle sequence (replacement is usually performed with a plurality of bus cycles) is output to the internal data bus. During cache replacement, the cache memory registers or writes the replacement data, that is, the data read from the external main memory is stored in the cache memory.
In principle, the cache memory may be searched with the address which caused the cache miss, upon completion of cache replacement. However, since data for the access which caused the cache miss is transferred directly to the instruction decoding unit during and after cache replacement, cache memory is searched with the address updated for only the most recent access.
As mentioned above, a conventional microprocessor with incorporated cache memory processes replacement data (such as decoding of instruction) for no more than one access at the same time as it registers data to cache memory so as to reduce overhead in replacement. For example, therefore, when there are replacement data for the last four accesses, the replacement data for the three oldest accesses must be retrieved again with the cache memory after replacement. This cannot improve overhead so much. In addition, the prefetch pointer must output the replacement address to the cache memory during cache memory replacement. If more data needs to be processed after the first access, the contents of the prefetch pointer storing the replacement address must be updated for data processing after completion of each replacement. This complicates the processing and delays the next access to the cache memory after replacement by the amount of time required for address updating.